A 100-MS/s 4-MHz Bandwidth 77.3-dB SNDR ΔΣ ADC with a Triple Sampling Technique - researchr publication authors

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Yusuke Kanazawa, Yoshihisa Fujimoto, Pascal Lo Ré, Michael M. Miyamoto. A 100-MS/s 4-MHz Bandwidth 77.3-dB SNDR ΔΣ ADC with a Triple Sampling Technique. In Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, CICC 2006, DoubleTree Hotel, San Jose, California, USA, September 10-13, 2006. pages 53-56, IEEE, 2006. [doi]

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