A 100-MS/s 4-MHz Bandwidth 77.3-dB SNDR ΔΣ ADC with a Triple Sampling Technique

Yusuke Kanazawa, Yoshihisa Fujimoto, Pascal Lo Ré, Michael M. Miyamoto. A 100-MS/s 4-MHz Bandwidth 77.3-dB SNDR ΔΣ ADC with a Triple Sampling Technique. In Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, CICC 2006, DoubleTree Hotel, San Jose, California, USA, September 10-13, 2006. pages 53-56, IEEE, 2006. [doi]

@inproceedings{KanazawaFRM06,
  title = {A 100-MS/s 4-MHz Bandwidth 77.3-dB SNDR ΔΣ ADC with a Triple Sampling Technique},
  author = {Yusuke Kanazawa and Yoshihisa Fujimoto and Pascal Lo Ré and Michael M. Miyamoto},
  year = {2006},
  doi = {10.1109/CICC.2006.320962},
  url = {http://dx.doi.org/10.1109/CICC.2006.320962},
  researchr = {https://researchr.org/publication/KanazawaFRM06},
  cites = {0},
  citedby = {0},
  pages = {53-56},
  booktitle = {Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, CICC 2006, DoubleTree Hotel, San Jose, California, USA, September 10-13, 2006},
  publisher = {IEEE},
  isbn = {1-4244-0075-9},
}