The following publications are possibly variants of this publication:
- A new approach to logic synthesis of multi-output boolean functions on pal-based CPLDSDariusz Kania. glvlsi 2007: 152-155 [doi]
- Decomposition-based logic synthesis for PAL-based CPLDsAdam Opara, Dariusz Kania. amcs, 20(2):367-384, 2010. [doi]
- Logic synthesis for PAL-based CPLD-s based on two-stage decompositionDariusz Kania, Józef Kulisz. jss, 80(7):1129-1141, 2007. [doi]
- Two-Level Logic Synthesis on PAL-Based CPLD and FPGA Using DecompositionDariusz Kania. euromicro 1999: 1278-1281 [doi]
- Logic synthesis based on decomposition for CPLDsDariusz Kania, Adam Milik. mam, 34(1):25-38, 2010. [doi]
- Logic Decomposition for PAL-Based CPLDsDariusz Kania. jcsc, 24(3), 2015. [doi]
- Decomposition of Multi-Output Functions for CPLDsDariusz Kania, Adam Milik, Józef Kulisz. dsdm 2005: 442-449 [doi]
- Area and speed oriented synthesis of FSMs for PAL-based CPLDsRobert Czerwinski, Dariusz Kania. mam, 36(1):45-61, 2012. [doi]
- State Assignment for PAL-based CPLDsRobert Czerwinski, Dariusz Kania. dsdm 2005: 127-134 [doi]