R. Kannan, R. Rangarajan. Low power noise immune node voltage comparison keeper design for high speed architectures. Microprocessors and Microsystems, 77:103192, 2020. [doi]
@article{KannanR20-0,
title = {Low power noise immune node voltage comparison keeper design for high speed architectures},
author = {R. Kannan and R. Rangarajan},
year = {2020},
doi = {10.1016/j.micpro.2020.103192},
url = {https://doi.org/10.1016/j.micpro.2020.103192},
researchr = {https://researchr.org/publication/KannanR20-0},
cites = {0},
citedby = {0},
journal = {Microprocessors and Microsystems},
volume = {77},
pages = {103192},
}