Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs

Yusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Yasuhisa Shimazaki, Tadashi Hoshi, Yujiro Miyairi, Toshifumi Ishii, Tetsuya Yamada, Takahiro Irita, Toshihiro Hattori, Kazumasa Yanagisawa, Naohiko Irie. Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs. J. Solid-State Circuits, 42(1):74-83, 2007. [doi]

@article{KannoMYHSHMIYIH07,
  title = {Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs},
  author = {Yusuke Kanno and Hiroyuki Mizuno and Yoshihiko Yasu and Kenji Hirose and Yasuhisa Shimazaki and Tadashi Hoshi and Yujiro Miyairi and Toshifumi Ishii and Tetsuya Yamada and Takahiro Irita and Toshihiro Hattori and Kazumasa Yanagisawa and Naohiko Irie},
  year = {2007},
  doi = {10.1109/JSSC.2006.885057},
  url = {https://doi.org/10.1109/JSSC.2006.885057},
  researchr = {https://researchr.org/publication/KannoMYHSHMIYIH07},
  cites = {0},
  citedby = {0},
  journal = {J. Solid-State Circuits},
  volume = {42},
  number = {1},
  pages = {74-83},
}