Min-Sheng Kao, Jen-Ming Wu, Chih-Hsing Lin, Fanta Chen, Ching-Te Chiu, Shawn S. H. Hsu. A 10-Gb/s CML I/O Circuit for Backplane Interconnection in 0.18- /mu m CMOS Technology. IEEE Trans. VLSI Syst., 17(5):688-696, 2009. [doi]
@article{KaoWLCCH09,
title = {A 10-Gb/s CML I/O Circuit for Backplane Interconnection in 0.18- /mu m CMOS Technology},
author = {Min-Sheng Kao and Jen-Ming Wu and Chih-Hsing Lin and Fanta Chen and Ching-Te Chiu and Shawn S. H. Hsu},
year = {2009},
doi = {10.1109/TVLSI.2009.2016726},
url = {http://dx.doi.org/10.1109/TVLSI.2009.2016726},
researchr = {https://researchr.org/publication/KaoWLCCH09},
cites = {0},
citedby = {0},
journal = {IEEE Trans. VLSI Syst.},
volume = {17},
number = {5},
pages = {688-696},
}