Design Optimization of MV-NMOS to Improve Holding Voltage of a 28nm CMOS Technology ESD Power Clamp

Sagar Premnath Karalkar, Vishal Ganesan, Milova Paul, Kyong Jin Hwang, Robert Gauthier. Design Optimization of MV-NMOS to Improve Holding Voltage of a 28nm CMOS Technology ESD Power Clamp. In IEEE International Reliability Physics Symposium, IRPS 2021, Monterey, CA, USA, March 21-25, 2021. pages 1-5, IEEE, 2021. [doi]

Abstract

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