A Formal Verification Method of Scheduling in High-level Synthesis

Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota, Chris Reade. A Formal Verification Method of Scheduling in High-level Synthesis. In 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA. pages 71-78, IEEE Computer Society, 2006. [doi]

@inproceedings{KarfaMSPR06,
  title = {A Formal Verification Method of Scheduling in High-level Synthesis},
  author = {Chandan Karfa and Chittaranjan A. Mandal and Dipankar Sarkar and S. R. Pentakota and Chris Reade},
  year = {2006},
  doi = {10.1109/ISQED.2006.10},
  url = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2006.10},
  researchr = {https://researchr.org/publication/KarfaMSPR06},
  cites = {0},
  citedby = {0},
  pages = {71-78},
  booktitle = {7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA},
  publisher = {IEEE Computer Society},
  isbn = {0-7695-2523-7},
}