Thermal-Safe Schedule Generation for System-on-Chip Testing

Rajit Karmakar, Santanu Chattopadhyay. Thermal-Safe Schedule Generation for System-on-Chip Testing. In 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, VLSID 2016, Kolkata, India, January 4-8, 2016. pages 475-480, IEEE Computer Society, 2016. [doi]

@inproceedings{KarmakarC16,
  title = {Thermal-Safe Schedule Generation for System-on-Chip Testing},
  author = {Rajit Karmakar and Santanu Chattopadhyay},
  year = {2016},
  doi = {10.1109/VLSID.2016.47},
  url = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2016.47},
  researchr = {https://researchr.org/publication/KarmakarC16},
  cites = {0},
  citedby = {0},
  pages = {475-480},
  booktitle = {29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, VLSID 2016, Kolkata, India, January 4-8, 2016},
  publisher = {IEEE Computer Society},
  isbn = {978-1-4673-8700-2},
}