State Assignment for Realizing Modular Input-Free Sequential Logical Networks Without Invertors

Svetlana P. Kartashev. State Assignment for Realizing Modular Input-Free Sequential Logical Networks Without Invertors. J. Comput. Syst. Sci., 7(5):522-542, 1973.

@article{Kartashev73,
  title = {State Assignment for Realizing Modular Input-Free Sequential Logical Networks Without Invertors},
  author = {Svetlana P. Kartashev},
  year = {1973},
  researchr = {https://researchr.org/publication/Kartashev73},
  cites = {0},
  citedby = {0},
  journal = {J. Comput. Syst. Sci.},
  volume = {7},
  number = {5},
  pages = {522-542},
}