The following publications are possibly variants of this publication:
- PSP: Parallel sub-pipelined architecture for high throughput AES on FPGA and ASICK. Rahimunnisa, P. Karthigaikumar, N. Anitha Christy, S. Suresh Kumar, J. Jayakumar. cejcs, 3(4):173-186, 2013. [doi]
- An Efficient Hardware Architecture for High Throughput AES Encryptor Using MUX Based Sub Pipelined S-BoxS. Sridevi Sathya Priya, P. Karthigaikumar, N. M. Siva Mangai, P. Kirti Gaurav Das. wpc, 94(4):2259-2273, 2017. [doi]