S. Sridevi Sathya Priya - researchr alias

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Viewing Publication 1 - 7 from 7

2023

Design of INV/BUFF Logic Locking For Enhancing the Hardware SecurityNaveenkumar R, N. M. Sivamangai, Napolean A, S. Sridevi Sathya Priya, S. V. Ashika. et, 39(2):141-153, April 2023. [doi]

Analysis of Various Visual Cryptographic Techniques and their Issues Based on Optimization AlgorithmsA. S. Sajitha, S. Sridevi Sathya Priya. ijig, 23(6), November 2023. [doi]

2022

Design and Evaluation of XOR Arbiter Physical Unclonable Function and its Implementation on FPGA in Hardware Security ApplicationsNaveenkumar R, N. M. Sivamangai, Napolean A, S. Sridevi Sathya Priya. et, 38(6):653-666, December 2022. [doi]

2017

High Throughput AES Algorithm Using Parallel Subbytes and MixColumnS. Sridevi Sathya Priya, P. Karthigaikumar, N. M. Siva Mangai, V. Rejula. wpc, 95(2):1433-1449, 2017. [doi]

An Efficient Hardware Architecture for High Throughput AES Encryptor Using MUX Based Sub Pipelined S-BoxS. Sridevi Sathya Priya, P. Karthigaikumar, N. M. Siva Mangai, P. Kirti Gaurav Das. wpc, 94(4):2259-2273, 2017. [doi]

2015

Efficient hardware implementation of AES algorithm using bio metric keyS. Sridevi Sathya Priya, P. Karthigaikumar, N. M. Siva Mangai, R. Sandhya. ijict, 7(4/5):437-454, 2015. [doi]

2012

Survey on Efficient, Low-power, AES Image Encryption and Bio-cryptography SchemesS. Sridevi Sathya Priya, P. Karthigaikumar, N. M. Siva Mangai, P. T. Vanathi. smartcr, 2(6):379-390, 2012. [doi]

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