An Efficient Hardware Architecture for High Throughput AES Encryptor Using MUX Based Sub Pipelined S-Box - researchr publication

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S. Sridevi Sathya Priya, P. Karthigaikumar, N. M. Siva Mangai, P. Kirti Gaurav Das. An Efficient Hardware Architecture for High Throughput AES Encryptor Using MUX Based Sub Pipelined S-Box. Wireless Personal Communications, 94(4):2259-2273, 2017. [doi]

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