Evaluating architecture and compiler design through static loop analysis

Yuriy Kashnikov, Pablo de Oliveira Castro, Emmanuel Oseret, William Jalby. Evaluating architecture and compiler design through static loop analysis. In International Conference on High Performance Computing & Simulation, HPCS 2013, Helsinki, Finland, July 1-5, 2013. pages 535-544, IEEE, 2013. [doi]

@inproceedings{KashnikovCOJ13-0,
  title = {Evaluating architecture and compiler design through static loop analysis},
  author = {Yuriy Kashnikov and Pablo de Oliveira Castro and Emmanuel Oseret and William Jalby},
  year = {2013},
  doi = {10.1109/HPCSim.2013.6641465},
  url = {http://dx.doi.org/10.1109/HPCSim.2013.6641465},
  researchr = {https://researchr.org/publication/KashnikovCOJ13-0},
  cites = {0},
  citedby = {0},
  pages = {535-544},
  booktitle = {International Conference on High Performance Computing & Simulation, HPCS 2013, Helsinki, Finland, July 1-5, 2013},
  publisher = {IEEE},
  isbn = {978-1-4799-0836-3},
}