Raghava Katreepalli, Themistoklis Haniotakis. Power efficient synchronous counter design. Computers & Electrical Engineering, 75:288-300, 2019. [doi]
@article{KatreepalliH19,
title = {Power efficient synchronous counter design},
author = {Raghava Katreepalli and Themistoklis Haniotakis},
year = {2019},
doi = {10.1016/j.compeleceng.2018.01.001},
url = {https://doi.org/10.1016/j.compeleceng.2018.01.001},
researchr = {https://researchr.org/publication/KatreepalliH19},
cites = {0},
citedby = {0},
journal = {Computers & Electrical Engineering},
volume = {75},
pages = {288-300},
}