A variation aware timing model for a 2-input NAND gate and its use in sub-65 nm CMOS standard cell characterization - researchr publication

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Baljit Kaur, Arvind Sharma, Naushad Alam, S. K. Manhas, Bulusu Anand. A variation aware timing model for a 2-input NAND gate and its use in sub-65 nm CMOS standard cell characterization. Microelectronics Journal, 53:45-55, 2016. [doi]

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