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An FPGA Implementation for a Flexible-Length-Arithmetic Processor Employing the FDFM Processor Core Approach

Tatsuya Kawamoto, Xin Zhou, Jacir Luiz Bordim, Yasuaki Ito, Koji Nakano. An FPGA Implementation for a Flexible-Length-Arithmetic Processor Employing the FDFM Processor Core Approach. IEICE Transactions, 99-D(12):2901-2910, 2016. [doi]

Authors

Tatsuya Kawamoto

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Xin Zhou

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Jacir Luiz Bordim

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Yasuaki Ito

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Koji Nakano

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