Tatsuya Kawamoto, Xin Zhou, Jacir Luiz Bordim, Yasuaki Ito, Koji Nakano. An FPGA Implementation for a Flexible-Length-Arithmetic Processor Employing the FDFM Processor Core Approach. IEICE Transactions, 99-D(12):2901-2910, 2016. [doi]
@article{KawamotoZBIN16,
title = {An FPGA Implementation for a Flexible-Length-Arithmetic Processor Employing the FDFM Processor Core Approach},
author = {Tatsuya Kawamoto and Xin Zhou and Jacir Luiz Bordim and Yasuaki Ito and Koji Nakano},
year = {2016},
url = {http://search.ieice.org/bin/summary.php?id=e99-d_12_2901},
researchr = {https://researchr.org/publication/KawamotoZBIN16},
cites = {0},
citedby = {0},
journal = {IEICE Transactions},
volume = {99-D},
number = {12},
pages = {2901-2910},
}