A 100-MHz 51.2-Gb/s packet lookup engine LSI based on missmatch detection circuit combined with linked-list hash table

Yoshifumi Kawamura, Kousuke Imamura, Naoki Miura, Masami Urano, Satoshi Shigematsu, Yoshio Matsuda. A 100-MHz 51.2-Gb/s packet lookup engine LSI based on missmatch detection circuit combined with linked-list hash table. In 2015 International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2015, Nusa Dua Bali, Indonesia, November 9-12, 2015. pages 351-356, IEEE, 2015. [doi]

Abstract

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