ESD protection circuit for high-voltage CMOS ICs with improved immunity against transient-induced latchup

Ming-Dou Ker, Che-Lun Hsu, Wen-Yi Chen. ESD protection circuit for high-voltage CMOS ICs with improved immunity against transient-induced latchup. In International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France. pages 989-992, IEEE, 2010. [doi]

Abstract

Abstract is missing.