Reversible Realization of Quaternary Decoder, Multiplexer, and Demultiplexer Circuits - researchr publication related

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Mozammel H. A. Khan. Reversible Realization of Quaternary Decoder, Multiplexer, and Demultiplexer Circuits. In 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 22-23 May 2008, Dallas, Texas, USA. pages 208-213, IEEE Computer Society, 2008. [doi]

The following publications are possibly variants of this publication:

Reversible Realization of Quaternary Decoder, Multiplexer, and Demultiplexer CircuitsMozammel H. A. Khan. engl, 15(2):203-207, 2007. [doi]

Scalable Architectures for Design of Reversible Quaternary Multiplexer and Demultiplexer CircuitsMozammel H. A. Khan. ismvl 2009: 343-348 [doi]

Design of Reversible/Quantum Ternary Multiplexer and DemultiplexerMozammel H. A. Khan. engl, 13(2):65-69, 2006.

GF(4) Based Synthesis of Quaternary Reversible/Quantum Logic CircuitsMozammel H. A. Khan, Marek A. Perkowski. mvl, 13(4-6):583-604, 2007. [doi]

GF(4) Based Synthesis of Quaternary Reversible/Quantum Logic CircuitsMozammel H. A. Khan, Marek A. Perkowski. ismvl 2007: 11 [doi]

Reversible Logic Based Mapping of Quaternary Sequential Circuits Using QGFSOP ExpressionMozammel H. A. Khan, Himanshu Thapliyal. isvlsi 2015: 297-302 [doi]

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