A Low Speed Digital Correlator Architecture Optimized For Resource Savings - researchr publication authors

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Jehangir Khan, Yassin Elhillali, Smaïl Niar, Atika Rivenq. A Low Speed Digital Correlator Architecture Optimized For Resource Savings. In Gilles Sassatelli, Leandro Soares Indrusiak, Manfred Glesner, Lionel Torres, editors, Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2006, Montpellier, France, July 2006. pages 207-213, Univ. Montpellier II, 2006.

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