Jehangir Khan, Yassin Elhillali, Smaïl Niar, Atika Rivenq. A Low Speed Digital Correlator Architecture Optimized For Resource Savings. In Gilles Sassatelli, Leandro Soares Indrusiak, Manfred Glesner, Lionel Torres, editors, Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2006, Montpellier, France, July 2006. pages 207-213, Univ. Montpellier II, 2006.
@inproceedings{KhanENR06,
title = {A Low Speed Digital Correlator Architecture Optimized For Resource Savings},
author = {Jehangir Khan and Yassin Elhillali and Smaïl Niar and Atika Rivenq},
year = {2006},
tags = {optimization, architecture},
researchr = {https://researchr.org/publication/KhanENR06},
cites = {0},
citedby = {0},
pages = {207-213},
booktitle = {Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2006, Montpellier, France, July 2006},
editor = {Gilles Sassatelli and Leandro Soares Indrusiak and Manfred Glesner and Lionel Torres},
publisher = {Univ. Montpellier II},
isbn = {2-9517461-2-1},
}