An Evaluation on the Accuracy of the Minimum-Width Transistor Area Models in Ranking the Layout Area of FPGA Architectures

Farheen Fatima Khan, Andy Ye. An Evaluation on the Accuracy of the Minimum-Width Transistor Area Models in Ranking the Layout Area of FPGA Architectures. TRETS, 11(1), 2018. [doi]

Authors

Farheen Fatima Khan

This author has not been identified. Look up 'Farheen Fatima Khan' in Google

Andy Ye

This author has not been identified. Look up 'Andy Ye' in Google