Gargi Khanna, Rajeevan Chandel, Ashwani Kumar Chandel. Impact of skew and jitter on the performance of VLSI interconnects. In 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2010, Kuala Lumpur, Malaysia, December 6-9, 2010. pages 1223-1226, IEEE, 2010. [doi]
@inproceedings{KhannaCC10,
title = {Impact of skew and jitter on the performance of VLSI interconnects},
author = {Gargi Khanna and Rajeevan Chandel and Ashwani Kumar Chandel},
year = {2010},
doi = {10.1109/APCCAS.2010.5775007},
url = {http://dx.doi.org/10.1109/APCCAS.2010.5775007},
researchr = {https://researchr.org/publication/KhannaCC10},
cites = {0},
citedby = {0},
pages = {1223-1226},
booktitle = {2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2010, Kuala Lumpur, Malaysia, December 6-9, 2010},
publisher = {IEEE},
isbn = {978-1-4244-7454-7},
}