Hamid Reza Kheirabadi, Morteza Saheb Zamani. An efficient net ordering algorithm for buffer insertion. In Hai Zhou, Enrico Macii, Zhiyuan Yan, Yehia Massoud, editors, Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007. pages 521-524, ACM, 2007. [doi]
@inproceedings{KheirabadiZ07,
title = {An efficient net ordering algorithm for buffer insertion},
author = {Hamid Reza Kheirabadi and Morteza Saheb Zamani},
year = {2007},
doi = {10.1145/1228784.1228908},
url = {http://doi.acm.org/10.1145/1228784.1228908},
researchr = {https://researchr.org/publication/KheirabadiZ07},
cites = {0},
citedby = {0},
pages = {521-524},
booktitle = {Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007},
editor = {Hai Zhou and Enrico Macii and Zhiyuan Yan and Yehia Massoud},
publisher = {ACM},
isbn = {978-1-59593-605-9},
}