Determination of the stress level for voltage screen of integrated circuits

R. M. Kho, A. J. Moonen, V. M. Girault, Jaap Bisschop, E. H. T. Olthof, S. Nath, Z. N. Liang. Determination of the stress level for voltage screen of integrated circuits. Microelectronics Reliability, 50(9-11):1210-1214, 2010. [doi]

@article{KhoMGBONL10,
  title = {Determination of the stress level for voltage screen of integrated circuits},
  author = {R. M. Kho and A. J. Moonen and V. M. Girault and Jaap Bisschop and E. H. T. Olthof and S. Nath and Z. N. Liang},
  year = {2010},
  doi = {10.1016/j.microrel.2010.07.103},
  url = {http://dx.doi.org/10.1016/j.microrel.2010.07.103},
  researchr = {https://researchr.org/publication/KhoMGBONL10},
  cites = {0},
  citedby = {0},
  journal = {Microelectronics Reliability},
  volume = {50},
  number = {9-11},
  pages = {1210-1214},
}