A partial scan methodology for testing self-timed circuits

Ajay Khoche, Erik Brunvand. A partial scan methodology for testing self-timed circuits. In 13th IEEE VLSI Test Symposium (VTS 95), April 30 - May 3, 1995, Princeton, New Jersey, USA. pages 283-289, IEEE Computer Society, 1995. [doi]

Abstract

Abstract is missing.