A 40 nm 222 mW H.264 Full-HD Decoding, 25 Power Domains, 14-Core Application Processor With x512b Stacked DRAM

Yu Kikuchi, Makoto Takahashi, Tomohisa Maeda, Masatoshi Fukuda, Yasuhiro Koshio, Hiroyuki Hara, Hideho Arakida, Hideaki Yamamoto, Yousuke Hagiwara, Tetsuya Fujita, Manabu Watanabe, Hirokazu Ezawa, Takayoshi Shimazawa, Yasuo Ohara, Takashi Miyamori, Mototsugu Hamada, Masafumi Takahashi, Yukihito Oowaki. A 40 nm 222 mW H.264 Full-HD Decoding, 25 Power Domains, 14-Core Application Processor With x512b Stacked DRAM. J. Solid-State Circuits, 46(1):32-41, 2011. [doi]

@article{KikuchiTMFKHAYHFWESOMHTO11,
  title = {A 40 nm 222 mW H.264 Full-HD Decoding, 25 Power Domains, 14-Core Application Processor With x512b Stacked DRAM},
  author = {Yu Kikuchi and Makoto Takahashi and Tomohisa Maeda and Masatoshi Fukuda and Yasuhiro Koshio and Hiroyuki Hara and Hideho Arakida and Hideaki Yamamoto and Yousuke Hagiwara and Tetsuya Fujita and Manabu Watanabe and Hirokazu Ezawa and Takayoshi Shimazawa and Yasuo Ohara and Takashi Miyamori and Mototsugu Hamada and Masafumi Takahashi and Yukihito Oowaki},
  year = {2011},
  doi = {10.1109/JSSC.2010.2079370},
  url = {http://dx.doi.org/10.1109/JSSC.2010.2079370},
  researchr = {https://researchr.org/publication/KikuchiTMFKHAYHFWESOMHTO11},
  cites = {0},
  citedby = {0},
  journal = {J. Solid-State Circuits},
  volume = {46},
  number = {1},
  pages = {32-41},
}