A VLSI Design of High Speed Bit-level Viterbi Decoder

Min Woo Kim, Jun Dong Cho. A VLSI Design of High Speed Bit-level Viterbi Decoder. In IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006. pages 309-312, IEEE, 2006. [doi]

Authors

Min Woo Kim

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Jun Dong Cho

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