Min Woo Kim, Jun Dong Cho. A VLSI Design of High Speed Bit-level Viterbi Decoder. In IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006. pages 309-312, IEEE, 2006. [doi]
@inproceedings{KimC06:37, title = {A VLSI Design of High Speed Bit-level Viterbi Decoder}, author = {Min Woo Kim and Jun Dong Cho}, year = {2006}, doi = {10.1109/APCCAS.2006.342413}, url = {http://dx.doi.org/10.1109/APCCAS.2006.342413}, tags = {design}, researchr = {https://researchr.org/publication/KimC06%3A37}, cites = {0}, citedby = {0}, pages = {309-312}, booktitle = {IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006}, publisher = {IEEE}, }