A VLSI Design of High Speed Bit-level Viterbi Decoder

Min Woo Kim, Jun Dong Cho. A VLSI Design of High Speed Bit-level Viterbi Decoder. In IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006. pages 309-312, IEEE, 2006. [doi]

Abstract

Abstract is missing.