Performance optimization by gate sizing and path sensitization

Juho Kim, David Hung-Chang Du. Performance optimization by gate sizing and path sensitization. IEEE Trans. on CAD of Integrated Circuits and Systems, 17(5):459-462, 1998. [doi]

@article{KimD98:0,
  title = {Performance optimization by gate sizing and path sensitization},
  author = {Juho Kim and David Hung-Chang Du},
  year = {1998},
  doi = {10.1109/43.703945},
  url = {http://doi.ieeecomputersociety.org/10.1109/43.703945},
  tags = {optimization},
  researchr = {https://researchr.org/publication/KimD98%3A0},
  cites = {0},
  citedby = {0},
  journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
  volume = {17},
  number = {5},
  pages = {459-462},
}