Sung Kim, Morteza Fayazi, Alhad Daftardar, Kuan-Yu Chen, Jielun Tan, Subhankar Pal, Tutu Ajayi, Yan Xiong, Trevor N. Mudge, Chaitali Chakrabarti, David T. Blaauw, Ronald G. Dreslinski, Hun-Seok Kim. Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory. J. Solid-State Circuits, 57(4):986-998, 2022. [doi]
@article{KimFDCTPAXMCBDK22,
title = {Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory},
author = {Sung Kim and Morteza Fayazi and Alhad Daftardar and Kuan-Yu Chen and Jielun Tan and Subhankar Pal and Tutu Ajayi and Yan Xiong and Trevor N. Mudge and Chaitali Chakrabarti and David T. Blaauw and Ronald G. Dreslinski and Hun-Seok Kim},
year = {2022},
doi = {10.1109/JSSC.2022.3140241},
url = {https://doi.org/10.1109/JSSC.2022.3140241},
researchr = {https://researchr.org/publication/KimFDCTPAXMCBDK22},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {57},
number = {4},
pages = {986-998},
}