Sung Kim, Morteza Fayazi, Alhad Daftardar, Kuan-Yu Chen, Jielun Tan, Subhankar Pal, Tutu Ajayi, Yan Xiong, Trevor N. Mudge, Chaitali Chakrabarti, David T. Blaauw, Ronald G. Dreslinski, Hun-Seok Kim. Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory. J. Solid-State Circuits, 57(4):986-998, 2022. [doi]
Abstract is missing.