Changhyun Kim, Kye-Hyun Kyung, W.-P. Jeong, J. S. Kim, Byung-Sik Moon, Joon-Wan Chai, S.-M. Yim, Jung Hwan Choi, K. H. Han, C. J. Park, Hong-Sun Hwang, H. Choi, Sung-Burn Cho, Clemenz L. Portmann, Soo-In Cho. A 2.5-V, 72-Mbit, 2.0-GByte/s packet-based DRAM with a 1.0-Gbps/pin interface. J. Solid-State Circuits, 34(5):645-652, 1999. [doi]
Abstract is missing.