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Bongjin Kim, In-Cheol Park. QC-LDPC Decoding Architecture based on Stride Scheduling. In International Symposium on Circuits and Systems (ISCAS 2011), May 15-19 2011, Rio de Janeiro, Brazil. pages 1319-1322, IEEE, 2011. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: Area-Efficient QC-LDPC Decoder Architecture Based on Stride Scheduling and Memory Bank DivisionBongjin Kim, In-Cheol Park. ieicet, 96-B(7):1772-1779, 2013. [doi] Scheduling algorithm for partially parallel architecture of LDPC decoder by matrix permutationIn-Cheol Park, Se-Hyeon Kang. iscas 2005: 5778-5781 [doi] Multi-Mode QC-LDPC Decoding Architecture With Novel Memory Access Scheduling for 5G New-Radio StandardSeongjin Lee, Sangsoo Park, Boseon Jang, In-Cheol Park. tcasI, 69(5):2035-2048, 2022. [doi]
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