An 18.24-Gb/s, 0.93-pJ/bit Receiver With an Input-Level-Sensing CDR Using Clock-Embedded C-PHY Signaling Over Trio Wires

Tae-Jin Kim, Jae-Woo Park, Hyun-Wook Lim, Jae-Youl Lee, Jung-Hoon Chun. An 18.24-Gb/s, 0.93-pJ/bit Receiver With an Input-Level-Sensing CDR Using Clock-Embedded C-PHY Signaling Over Trio Wires. J. Solid-State Circuits, 57(3):932-941, 2022. [doi]

Authors

Tae-Jin Kim

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Jae-Woo Park

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Hyun-Wook Lim

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Jae-Youl Lee

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Jung-Hoon Chun

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