Tae-Jin Kim, Jae-Woo Park, Hyun-Wook Lim, Jae-Youl Lee, Jung-Hoon Chun. An 18.24-Gb/s, 0.93-pJ/bit Receiver With an Input-Level-Sensing CDR Using Clock-Embedded C-PHY Signaling Over Trio Wires. J. Solid-State Circuits, 57(3):932-941, 2022. [doi]
@article{KimPLLC22,
title = {An 18.24-Gb/s, 0.93-pJ/bit Receiver With an Input-Level-Sensing CDR Using Clock-Embedded C-PHY Signaling Over Trio Wires},
author = {Tae-Jin Kim and Jae-Woo Park and Hyun-Wook Lim and Jae-Youl Lee and Jung-Hoon Chun},
year = {2022},
doi = {10.1109/JSSC.2021.3140053},
url = {https://doi.org/10.1109/JSSC.2021.3140053},
researchr = {https://researchr.org/publication/KimPLLC22},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {57},
number = {3},
pages = {932-941},
}