Jeongkyun Kim, Byungho Yook, Taemin Choi, Kyuwon Choi, Chanho Lee, Yunrong Li, Youngo Lee, Seok Yun, Changhoon Do, Hoyoung Tang, Inhak Lee, Dongwook Seo, Sangyeop Baeck. A 4.0GHz UHS Pseudo Two-port SRAM with BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4nm FinFET Technology. In 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, June 11-16, 2023. pages 1-2, IEEE, 2023. [doi]
Abstract is missing.