A 52-Gb/s ADC-Based PAM-4 Receiver With Comparator-Assisted 2-bit/Stage SAR ADC and Partially Unrolled DFE in 65-nm CMOS - researchr publication

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Shiva Kiran, Shengchang Cai, Ying Luo, Sebastian Hoyos, Samuel Palermo. A 52-Gb/s ADC-Based PAM-4 Receiver With Comparator-Assisted 2-bit/Stage SAR ADC and Partially Unrolled DFE in 65-nm CMOS. J. Solid-State Circuits, 54(3):659-671, 2019. [doi]

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