A 32 Gb/s ADC-Based PAM-4 Receiver with 2-bit/Stage SAR ADC and Partially-Unrolled DFE - researchr publication authors

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Shiva Kiran, Shengchang Cai, Ying Luo, Sebastian Hoyos, Samuel Palermo. A 32 Gb/s ADC-Based PAM-4 Receiver with 2-bit/Stage SAR ADC and Partially-Unrolled DFE. In IEEE Custom Integrated Circuits Conference, CICC 2019, Austin, TX, USA, April 14-17, 2019. pages 1-4, IEEE, 2019. [doi]

This author has not been identified. Look up 'Shiva Kiran' in GoogleThis author has not been identified. Look up 'Shengchang Cai' in GoogleThis author has not been identified. Look up 'Ying Luo' in GoogleThis author has not been identified. Look up 'Sebastian Hoyos' in GoogleThis author has not been identified. Look up 'Samuel Palermo' in Google

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