Peter J. Klim, John Barth, William R. Reohr, David Dick, Gregory Fredeman, Gary Koch, Hien M. Le, Aditya Khargonekar, Pamela Wilcox, John Golz, Jente B. Kuang, Abraham Mathews, Jethro C. Law, Trong Luong, Hung C. Ngo, Ryan Freese, Hillery C. Hunter, Erik Nelson, Paul C. Parries, Toshiaki Kirihata, Subramanian S. Iyer. A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS. J. Solid-State Circuits, 44(4):1216-1226, 2009. [doi]
@article{KlimBRDFKLKWGKM09,
title = {A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS},
author = {Peter J. Klim and John Barth and William R. Reohr and David Dick and Gregory Fredeman and Gary Koch and Hien M. Le and Aditya Khargonekar and Pamela Wilcox and John Golz and Jente B. Kuang and Abraham Mathews and Jethro C. Law and Trong Luong and Hung C. Ngo and Ryan Freese and Hillery C. Hunter and Erik Nelson and Paul C. Parries and Toshiaki Kirihata and Subramanian S. Iyer},
year = {2009},
doi = {10.1109/JSSC.2009.2014207},
url = {https://doi.org/10.1109/JSSC.2009.2014207},
researchr = {https://researchr.org/publication/KlimBRDFKLKWGKM09},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {44},
number = {4},
pages = {1216-1226},
}