Bit-Level systolic architectures for high performance IIR filtering

S. C. Knowles, John G. McWhirter, Roger F. Woods, John V. McCanny. Bit-Level systolic architectures for high performance IIR filtering. VLSI Signal Processing, 1(1):9-24, 1989. [doi]

@article{KnowlesMWM89,
  title = {Bit-Level systolic architectures for high performance IIR filtering},
  author = {S. C. Knowles and John G. McWhirter and Roger F. Woods and John V. McCanny},
  year = {1989},
  doi = {10.1007/BF00932062},
  url = {http://dx.doi.org/10.1007/BF00932062},
  tags = {architecture, C++},
  researchr = {https://researchr.org/publication/KnowlesMWM89},
  cites = {0},
  citedby = {0},
  journal = {VLSI Signal Processing},
  volume = {1},
  number = {1},
  pages = {9-24},
}