Short-circuit power driven gate sizing technique for reducing power dissipation

Uming Ko, Poras T. Balsara. Short-circuit power driven gate sizing technique for reducing power dissipation. IEEE Trans. VLSI Syst., 3(3):450-455, 1995. [doi]

@article{KoB95,
  title = {Short-circuit power driven gate sizing technique for reducing power dissipation},
  author = {Uming Ko and Poras T. Balsara},
  year = {1995},
  doi = {10.1109/92.407004},
  url = {http://doi.ieeecomputersociety.org/10.1109/92.407004},
  researchr = {https://researchr.org/publication/KoB95},
  cites = {0},
  citedby = {0},
  journal = {IEEE Trans. VLSI Syst.},
  volume = {3},
  number = {3},
  pages = {450-455},
}