Energy optimization of multi-level processor cache architectures - researchr publication authors

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Uming Ko, Poras T. Balsara, Ashwini K. Nanda. Energy optimization of multi-level processor cache architectures. In Massoud Pedram, Robert W. Brodersen, Kurt Keutzer, editors, Proceedings of the 1995 International Symposium on Low Power Design 1995, Dana Point, California, USA, April 23-26, 1995. pages 45-49, ACM, 1995. [doi]

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