Uming Ko, Poras T. Balsara, Ashwini K. Nanda. Energy optimization of multi-level processor cache architectures. In Massoud Pedram, Robert W. Brodersen, Kurt Keutzer, editors, Proceedings of the 1995 International Symposium on Low Power Design 1995, Dana Point, California, USA, April 23-26, 1995. pages 45-49, ACM, 1995. [doi]
@inproceedings{KoBN95,
title = {Energy optimization of multi-level processor cache architectures},
author = {Uming Ko and Poras T. Balsara and Ashwini K. Nanda},
year = {1995},
doi = {10.1145/224081.224090},
url = {http://doi.acm.org/10.1145/224081.224090},
tags = {optimization, caching, architecture},
researchr = {https://researchr.org/publication/KoBN95},
cites = {0},
citedby = {0},
pages = {45-49},
booktitle = {Proceedings of the 1995 International Symposium on Low Power Design 1995, Dana Point, California, USA, April 23-26, 1995},
editor = {Massoud Pedram and Robert W. Brodersen and Kurt Keutzer},
publisher = {ACM},
isbn = {0-89791-744-8},
}