3D IC Memory BIST Controller Allocation for Test Time Minimization Under Power Constraints - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

Yen-Chun Ko, Shih-Hsu Huang. 3D IC Memory BIST Controller Allocation for Test Time Minimization Under Power Constraints. In 26th IEEE Asian Test Symposium, ATS 2017, Taipei City, Taiwan, November 27-30, 2017. pages 260-265, IEEE Computer Society, 2017. [doi]

This author has not been identified. Look up 'Yen-Chun Ko' in GoogleThis author has not been identified. Look up 'Shih-Hsu Huang' in Google

runs on WebDSL