Abstract is missing.
- An Enhanced Boundary Scan Architecture for Inter-Die Interconnect Leakage Measurement in 2.5D and 3D PackagesPok Man Preston Law, Cheng-Wen Wu, Long-Yi Lin, Hao-Chiao Hong. 5-10 [doi]
- On-Chip Ring Oscillator Based Scheme for TSV Delay MeasurementSongwei Pei, Alrashdi Ahmed Rabehb, Song Jin. 11-16 [doi]
- Testing of Interconnect Defects in Memory Based Reconfigurable Logic Device (MRLD)Senling Wang, Yoshinobu Higami, Hiroshi Takahashi, Masayuki Sato, Mitsunori Katsu, Shoichi Sekiguchi. 17-22 [doi]
- Test Pattern Compression for Probabilistic CircuitsChih-Ming Chang, Kai-Jie Yang, James Chien-Mo Li, Hung Chen. 23-27 [doi]
- Test Compression with Single-Input Data Spreader and Multiple Test SessionsChang Wen Chen, Yi-Cheng Kong, Kuen-Jong Lee. 28-33 [doi]
- Test Compaction with Dynamic Updating of Faults for Coverage of Undetected Transition Fault SitesIrith Pomeranz. 34-39 [doi]
- A New Active IC Metering Technique Based on Locking Scan CellsAijiao Cui, Xuesen Qian, Gang Qu, Huawei Li. 40-45 [doi]
- Tree-Based Logic Encryption for Resisting SAT AttackYung-Chih Chen. 46-51 [doi]
- Intra-Die-Variation-Aware Side Channel Analysis for Hardware Trojan DetectionFakir Sharif Hossain, Tomokazu Yoneda, Michihiro Shintani, Michiko Inoue, Alex Orailoglu. 52-57 [doi]
- On Securing Scan Design from Scan-Based Side-Channel AttacksSatyadev Ahlawat, Darshit Vaghani, Jaynarayan T. Tudu, Virendra Singh. 58-63 [doi]
- An Incremental Aging Analysis Method Based on Delta Circuit Simulation TechniqueSi-Rong He, Nguyen Cao Qui, Yu-Hsuan Kuo, Chien-Nan Jimmy Liu. 64-69 [doi]
- Post-Silicon Test Flow for Aging PredictionZih-Huan Gao, Hau Hsu, Ting-Shuo Hsu, Jing-Jia Liou. 70-75 [doi]
- Cloud-Based PVT Monitoring System for IoT DevicesGuan-Hao Lian, Shi-Yu Huang, Wei-yi Chen. 76-81 [doi]
- A Critical Charge Model for Estimating the SET and SEU Sensitivity: A Muller C-Element Case StudyMarko S. Andjelkovic, Milos Krstic, Rolf Kraemer, Varadan Savulimedu Veeravalli, Andreas Steininger. 82-87 [doi]
- Design and Implementation of an EG-Pool Based FPGA Formatter with Temperature CompensationYang-Kai Huang, Kuan-Te Li, Chih-Lung Hsiao, Chia-An Lee, Jiun-Lang Huang, Terry Kuo. 88-93 [doi]
- SAR TDC Architecture with Self-Calibration Employing Trigger CircuitYuki Ozawa, Takashi Ida, Richen Jiang, Shotaro Sakurai, Seiya Takigami, Nobukazu Tsukiji, Ryoji Shiota, Haruo Kobayashi. 94-99 [doi]
- Bringing Fault-Tolerant GigaHertz-Computing to Space: A Multi-stage Software-Side Fault-Tolerance Approach for Miniaturized SpacecraftChristian M. Fuchs, Todor P. Stefanov, Nadia Murillo, Aske Plaat. 100-107 [doi]
- Identification of Efficient Clustering Techniques for Test Power Activity on the LayoutHarshad Dhotre, Stephan Eggersglüß, Rolf Drechsler. 108-113 [doi]
- Security Implications of Cyberphysical Flow-Based Microfluidic BiochipsJack Tang, Mohamed Ibrahim, Krishnendu Chakrabarty, Ramesh Karri. 115-120 [doi]
- How to Secure Scan Design Against Scan-Based Side-Channel Attacks?Wei Zhou, Aijiao Cui, Huawei Li, Gang Qu. 121-126 [doi]
- Structure-Oriented Test of Reconfigurable Scan NetworksDominik Ull, Michael A. Kochte, Hans-Joachim Wunderlich. 127-132 [doi]
- Compaction of a Transparent-Scan Sequence to Reduce the Fail Data Volume for Scan Chain FaultsIrith Pomeranz. 133-138 [doi]
- Architecture for Reliable Scan-Dump in the Presence of Multiple Asynchronous Clock Domains in FPGA SoCsAmitava Majumdar, Balakrishna Jayadev, Da Cheng, Albert Lin. 139-144 [doi]
- Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data CorruptionYucong Zhang, Stefan Holst, Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Jun Qian. 145-150 [doi]
- Deterministic Path Delay Measurement Using Short Cycle Test PatternKentaro Kato. 151-156 [doi]
- Cell-Aware ATPG to Improve Defect Coverage for FPGA IPs and Next Generation Zynq® MPSoCsSeetal Potluri, Aaron Mathew, Rambabu Nerukonda, Ismed Hartanto, Shahin Toutounchi. 157-162 [doi]
- Testing Clock Distribution NetworksSying-Jyan Wang, Hsiang-Hsueh Chen, Chin-Hung Lien, Katherine Shu-Min Li. 163-168 [doi]
- Test Coverage Analysis for Designs with Timing ExceptionsKun-Han Tsai, Srinivasan Gopalakrishnan. 169-174 [doi]
- Test and Reliability of Emerging Non-volatile MemoriesSaid Hamdioui, Peyman Pouyan, Huawei Li, Ying Wang, Arijit Raychowdhury, Insik Yoon. 175-183 [doi]
- Test and Debug Strategy for High Speed JESD204B Rx PHYSurya Piplani, Humberto Fonseca, Vivek Mohan Sharma, Daniele Cervini, David Hardisty. 184-188 [doi]
- Post Silicon Debugging of Electrical Bugs Using Trace BuffersKentaro Iwata, Amir Masoud Gharehbaghi, Mehdi B. Tahoori, Masahiro Fujita. 189-194 [doi]
- On Evaluating and Constraining Assertions Using Conflicts in Absent ScenariosHuina Chao, Huawei Li, Xiaoyu Song, Tiancheng Wang, Xiaowei Li. 195-200 [doi]
- Yield Enhancement by Repair Circuits for Ultra-Fine Pitch Stacked-Chip ConnectionsKeitaro Koga, Hiromitsu Awano, Makoto Ikeda. 201-205 [doi]
- Error-Tolerability Evaluation and Test for Images in Face Detection ApplicationsTong-Yu Hsieh, Tai-Ang Cheng, Chao-Ru Chen. 206-211 [doi]
- PADLOC: Physically-Aware Defect Localization and CharacterizationSoumya Mittal, R. D. (Shawn) Blanton. 212-218 [doi]
- Automatic Identification of Yield Limiting Layout Patterns Using Root Cause Deconvolution on Volume Scan Diagnosis DataWu-Tung Cheng, Randy Klingenberg, Brady Benware, Wu Yang, Manish Sharma, Geir Eide, Yue Tian, Sudhakar M. Reddy, Yan Pan, Sherwin Fernandes, Atul Chittora. 219-224 [doi]
- Scan Chain Diagnosis Based on Unsupervised Machine LearningYu Huang, Brady Benware, Randy Klingenberg, Huaxing Tang, Jayant Dsouza, Wu-Tung Cheng. 225-230 [doi]
- Using Cell Aware Diagnostic Patterns to Improve Diagnosis Resolution for Cell Internal DefectsHuaxing Tang, Arvind Jain, Sanil Kumark Pillai, Dharmesh Joshi, Shamitha Rao. 231-236 [doi]
- Automotive IC On-line Test Techniques and the Application of Deterministic ATPG-Based Runtime TestYoichi Maeda, Jun Matsushima, Ron Press. 237-241 [doi]
- Open Defect Detection with a Built-in Test Circuit by IDDT Appearance Time in CMOS ICsAyumu Kambara, Hiroyuki Yotsuyanagi, Daichi Miyoshi, Masaki Hashizume, Shyue-Kung Lu. 242-247 [doi]
- Design for Testability Technique of Reversible Logic Circuits Based on Exclusive TestingJoyati Mondal, Debesh Kumar Das. 248-253 [doi]
- Fault-Aware Page Address Remapping Techniques for Enhancing Yield and Reliability of Flash MemoriesShyue-Kung Lu, Shu-Chi Yu, Masaki Hashizume, Hiroyuki Yotsuyanagi. 254-259 [doi]
- 3D IC Memory BIST Controller Allocation for Test Time Minimization Under Power ConstraintsYen-Chun Ko, Shih-Hsu Huang. 260-265 [doi]
- A Heuristic Algorithm for Automatic Generation of March TestsXiaole Cui, Yichi Luo, Qiujun Lin, Xiaoxin Cui. 266-271 [doi]