Majority Logic Circuit Minimization Using Node Addition and Removal

Chang-Cheng Ko, Chia-Chun Lin, Yung-Chih Chen, Chun-Yao Wang. Majority Logic Circuit Minimization Using Node Addition and Removal. IEEE Trans. on CAD of Integrated Circuits and Systems, 41(3):642-655, 2022. [doi]

Abstract

Abstract is missing.